Delay circuit and delay synchronization loop device

ABSTRACT

A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line circuit, the transfer circuits controlling the transfer of the outputs of the delay units of the first delay line circuit to associated stages of the delay units of the second delay line circuit. The delay units of respective stages of the first delay line circuit inverting input signals. Each stage delay unit of the second delay line circuit includes a logic circuit receiving an output signal of the transfer circuit associated with the delay unit in question and an output signal of a preceding stage to send an output signal to a following stage. The duty ratio is rendered variable by independently selecting the rising edge of the input signal and a propagation path of the falling edge.

This is a continuation of application Ser. No. 11/580,111 filed Oct. 13,2006, which is a divisional of Ser. No. 10/901,220 filed Jul. 29, 2004,now U.S. Pat. No. 7,135,906, issued Nov. 14, 2006. The entire disclosureof the prior applications is hereby incorporated by reference.

FIELD OF THE INVENTION

This invention relates to a delay circuit and, more particularly, to adelay circuit preferably applied to a delay locked loop (DLL).

BACKGROUND OF THE INVENTION

FIG. 21 schematically shows an illustrative structure of a DLL (delaylock loop) used e.g. in a conventional DDRII/I-SDRAM (Double Delta RateII-Synchronous DRAM). Referring to FIG. 21, the DLL is made up by twocontrol circuits and two coarse delay lines CDL 10 having a variabledelay time. The control circuit is composed of a phase detector (P/D)12, also termed a phase comparator, and a counter 13. An output of areceiver 11, which receives complementary clock signals CLK and CLKB, issupplied to the coarse delay line CDL 10, output pairs O0 and E0 ofwhich are supplied to a fine delay line FDL 15, composed of a phaseinterpolator, for phase adjustment. A multiplexer 17 receives outputdata signals, not shown, in parallel, and selects and outputs the outputdata signal to a data terminal DQ, in synchronization with each of therising edge and the falling edge of a clock signal CLK_0, output fromthe fine delay line FDL 15. Meanwhile, a reference numeral 17 in FIG. 21collectively denotes a multiplexer (data multiplexer) for multiplexinginput parallel data signals (read data) on a serial data signal, basedon a clock signal CLK_0, and an output buffer for outputting data from adata output terminal DQ. A dummy circuit 18 is a dummy multiplexer forproducing a delay equivalent to the delay time of the multiplexer 17 inthe feedback route in the DLL circuit. The dummy circuit 18 outputs afeedback clock signal CLK_FDB which rises based on a rising edge of theclock signal CLK_0 and which falls based on a falling edge of the clocksignal CLK_0. Meanwhile, an input of the phase detector (P/D) 12 may bean internal signal 10 and a dummy buffer of the delay time equivalent tothat of the input buffer 11 may be provided between the dummy circuit 18and the phase detector (P/D) 12. Alternatively, the feedback clocksignal CLK_FDB may be delayed by the dummy circuit 18 by a delay valueequivalent to the delay time of the input buffer 11.

The phase detector (P/D) 12 compares the phase of the feedback clocksignal CLK_FDB, output from the dummy circuit 18, with the phase of theinput signal CLK (e.g. phase of the rising edge), and counts the resultof comparison from the phase detector (P/D) 12, with a counter 13, withthe phase lead being UP and the phase delay being DOWN). A selectioncircuit 14 decodes the count result by the counter 13 to generate acontrol signal, used for variably setting the delay time in the coarsedelay line CDL 10. Meanwhile, the phase interpolator of the fine delayline FDL 15 outputs an output signal of the phase (delay) prescribed bydivision of the phase difference (delay) of the inputs O0 and E0. It isnoted that a pair of signals, entered to the phase interpolator, arerepresented by an even signal (E0 of FIG. 21) and an odd signal (O0 ofFIG. 21).

In this DLL circuit, the propagation time of the data output DQ issynchronized with an integer number times one clock cycle time tCK ofthe input clock signal CLK. For example, if one clock period tCK islonger, as shown in FIG. 3A, the synchronization of the data DQ with theclock signal CLK is attained in one clock cycle (referred to as “1Tmode”).

If one clock period tCK is lesser than the intrinsic delay of the delaycircuit (smallest delay time), as shown in FIG. 3B, the synchronizationof the data DQ with the clock signal CLK is attained in two clock cycles(referred to as “2T mode”).

In the DLL circuit, employing a CMOS delay circuit, the shorter thepropagation time, the lesser become the timing variations relative tothe variations in the power supply, that is, jitter. As for the timingvariations, the following relation is valid:

(timing variations)∝(propagation time)×(level variations) and

(level variations)∝(current consumption)

where P∝Q means that P is proportionate to B.

FIG. 23 is a diagram showing a structure of a conventional coarse delayline (CDL) used in the DLL circuit shown e.g. in FIG. 21. Meanwhile, asfor the CDL, shown in FIG. 23, reference is made e.g. to the followingPatent Publication 1. Referring to FIG. 23, the CDL includes a delayline circuit, composed of inverters 201, 202, . . . and 217, and firstto eighth tristate inverters 221 to 228 which receive outputs of theodd-numbered stage inverters 201, 203, 205, . . . , and 215respectively. Outputs of the first and third stage tristate inverters221 and 223 are connected in common and supplied to the ninth tristateinverter 229. Outputs of the second and fourth stage tristate inverters222 and 224 are connected in common and supplied to the tenth tristateinverter 230. Outputs of the fifth and seventh tri-state inverters 225and 227 are connected in common and supplied to the eleventh tri-stateinverter 231, while outputs of the sixth and eighth tri-state inverters226 and 228 are connected in common and supplied to the twelfthtri-state inverter 232. Outputs of the ninth and eleventh tri-stateinverters 229 and 231 are connected in common and supplied to theeleventh tri-state inverter 233, while outputs of the tenth and twelfthtri-state inverters 230 and 232 are connected in common and supplied toan inverter 234. The inverters 233 and 234 output an even output E0 andan odd output O0, respectively. The eleventh and twelfth tri-stateinverters 231 and 232 have output control terminals for receiving theresult of logical sum operations of RF_4 and RF_8 by an OR circuit 243and the result of logical sum operations of RF_6 and RF_10 by an ORcircuit 244 respectively, while the ninth and tenth tri-state inverters229 and 230 have output control terminals for receiving the result oflogical sum operations of RF_12 and RF_16 by an OR circuit 241 and theresult of logical sum operations of RF_14 and RF_18 by an OR circuit 242respectively.

Meanwhile, the specifications of e.g. the DDR (Double Data Rate)-II/Iare such that the data output DQ is synchronized with both edges of aclock signal, and that the duty ratio of 45 to 55% is allowed for theinput clock signal CLK. In order to make it possible to attainsynchronization at the 1.5 clock cycle between the 1T mode and the 2Tmode, it becomes necessary to independently set the delay time for therise input and that for the fall input of the clock signals CLK in a DLLcircuit or the like. However, in the conventional coarse delay line CDL,shown in FIGS. 21 and 23, it is not possible to set the rise or fall ofthe output clock signal independently from the rising edge and thefalling edge of the input clock signal.

As a delay lock loop for independently setting the rise and fallingedges of an output clock signal from the rise and falling edges of theinput clock signal, respectively, there is known a configuration inwhich a coarse delay line CDL(R) 10 ₁ for rising edge adjustment and acoarse delay line CDL(L) 10 ₂ for falling edge adjustment, are provided,as shown for example in FIG. 22, and in which phase detectors 12 ₁ and12 ₂ and counters 13 ₁ and 13 ₂ are also provided as the controlcircuit. Meanwhile, as for the structure in which a pair of coarse delaylines CDL are provided for the rising edge and the falling edge,reference is made to e.g. the following Patent Publication 2.

In FIG. 22, fine delay lines (FDL) 15 ₁ and 15 ₂ are provided inassociation with the coarse delay lines for rising edge adjustmentCDL(R) 10 ₁ and with the coarse delay lines for falling edge adjustmentCDL(L) 10 ₂, and there is provided a multiplexer circuit 16 formultiplexing two outputs of the fine delay lines (FDL) 15 ₁ and 15 ₂into one signal. An output clock signal CLK_0 from the multiplexercircuit 16 is supplied to the data multiplexer 17 which outputs two data(readout data) per clock cycle from a data output terminal DQ, insynchronism with a rising edge and the falling edge of the clock signalCLK_0. Meanwhile, the reference numeral 17 in FIG. 22 indicates a dataoutput route for e.g. the multiplexer and the output buffer.

[Patent Document 1]

Japanese Patent Kokai Publication No. JP-P2003-91331A (FIGS. 1 and 7)

[Patent Document 2]

Japanese Patent Kokai Publication No. JP-P2003-101409A (FIG. 20)

SUMMARY OF THE DISCLOSURE

In the DLL circuit, shown in FIG. 22, two rows of delay line circuitsCDLs are needed for generating the different propagation time for therise and the fall of the clock signal CLK. This circuit structure needsan area almost twice as large as that of that shown in FIG. 21, whilethe operating current (current consumption) is nearly doubled.

Moreover, in the DLL circuit, shown in FIG. 22, the timing of the riseand the fall of the output clock signal CLK_0 is determined on the basisof the rise and the fall of the input clock signal CLK, while therelacks the function of prescribing the timing of the rise and the fall ofthe output clock signal based on the fall and the rise of an input clocksignal.

Accordingly, it is an object of the present invention to provide asimplified delay circuit, generating different propagation time for thesignal rise and fall to suppress or reduce the increase in the circuitarea or power consumption to realize low jitter and small area of thesynchronous delay loop (DLL).

It is another object of the present invention to provide a synchronousdelay loop circuit in which clock cycles needed for synchronization maybe variably switched by a simplified circuit structure.

The above and other objects are attained by a delay circuit inaccordance with one aspect of the present invention, comprising a firstdelay line circuit having a plurality of stages of delay units, a seconddelay line circuit having a plurality of stages of delay units, aplurality of transfer circuits provided in association with respectivestages of the delay units of the first delay line circuit, the transfercircuits receiving outputs of the stages of the delay units of the firstdelay line circuit to control the transfer of the outputs of the delayunits to associated stages of the delay units of the second delay linecircuit, the delay units of respective stages of the first delay linecircuit inverting input signals to the delay units and outputting theinverted signals, each stage delay unit of the second delay line circuitincluding a logic circuit receiving an output signal of the transfercircuit associated with the delay unit in question and an output signalof the delay unit preceding the delay unit in question and foroutputting the result of logical operations on the input signals to adownstream side.

According to the present invention, an edge of an input signal, suppliedto an input end of the first delay line circuit and propagated throughthe first delay line circuit, is supplied, through the transfer circuitselected by the input control signal, to one of the delay units formingthe second delay line circuit which is associated with the selectedtransfer circuit. The edge being propagated from the delay unit throughthe second delay line circuit towards an output so as to be output froman output end of the second delay line circuit. An edge of the outputsignal from the output end of the second delay line circuit is delayedfrom the timing of the associated edge of the input signal by an amountprescribed by the number of stages of the first and second delay linecircuits forming a propagation path determined by the selected transfercircuit and by the delay time of the transfer circuits.

According to the present invention, one of a plurality of the transfercircuits receiving outputs of odd-numbered stages of delay units of thefirst delay line circuit, is selected by a corresponding control signal.One of a plurality of transfer circuits receiving outputs ofeven-numbered stages of delay units of the first delay line circuit, isselected by a corresponding control signal. The rise timing and the falltiming of an output signal of the second delay line circuit are variablyset with respect to the rising and fall of the signal supplied to thefirst delay line circuit.

A delay circuit in another aspect of the present invention comprises adelay line circuit including a plurality of stages of delay units, afirst switch on/off controlled based on an input control signal, and asecond switch connected to an output of the delay unit of the stagenumber corresponding to the control signal, and turned on at a timepoint when the transition edge of the rise or fall of the input signalsupplied to the delay line circuit and propagated has traversed a numberof stages corresponding to the selection control signal, with the secondswitch causing transition of a common node from one logic value to theother logic value through the first switch in the on-state, a signalgenerating circuit connected to the common node to generate a risingsignal or a falling signal responsive to the transition of the commonnode, and a control circuit responsive to an input signal supplied tothe delay line circuit to set the common node to the one logic value bythe other transition, that is, the falling or rising, of the inputsignal. According to the present invention, one ends of a plurality ofthe second switches are connected to outputs of plural delay units ofrespective different stages of the delay line circuit so as to be on/offcontrolled are connected common to the common node, and the first switchreceiving the control signal and on/off controlled, is provided acrossthe power supply and the other end of each of the plural secondswitches.

According to the present invention, the delay unit of the delay linecircuit may be formed by an inverter circuit, a series circuit composedof the second switches connected to outputs of the odd-numbered delayunits and the first switches associated with the second switches may beconnected to a first common node provided for odd-numbered stages, aseries circuit composed of the second switches connected to the outputsof the even-numbered delay units and the first switches associated withthe second switches may be connected to a second common node providedfor even-numbered stages. The signal generating circuit may be providedfor each of the first and second common nodes, and the delay of therising and the delay of the output from the rising and fall of theinput, respectively, may be variable.

Another delay synchronous loop (DLL) device according to the presentinvention includes a variable delay circuit receiving an input signal,variably delaying the rise timing and the fall timing of the inputsignal to output the resultant signal, a multiplexing circuit foroutputting an output signal, the pulse width of which is determined bythe rising and the fall of the signal delayed by the variable delaycircuit, and a control circuit for comparing the rising phase and thefalling phase of the input signal to the rising phase and the fallingphase of the output signal to variably control the delay time of thevariable delay circuit based on the result of phase comparison. Themultiplexing circuit for switching between decision of the rise timingand the fall timing of the output signal based on the rise and the fallof a signal output from the variable delay circuit and decision of therise timing and the fall timing of the output signal based on the falland the rise of the signal output from the variable delay circuit, inaccordance with the input mode decision signal. The control circuitvaries the rise timing and the fall timing of the output signal in thevariable delay circuit, based on the result of phase comparison of therise of the input signal and the output signal and the fall of the inputsignal and the output signal, or varies the fall timing and the risetiming of the output signal in the variable delay circuit, based on theresult of phase comparison of the rise of the input signal and theoutput signal and the fall of the input signal and the output signal, inaccordance with the input mode decision signal.

A delay locked loop device for generating an internal clock signalsynchronized with an input clock signal, according to the presentinvention, comprises:

a first phase detection circuit for comparing the rising phase of theinput clock signal and the rising phase of the internal clock signal, asecond phase detection circuit for comparing the falling phase of theinput clock signal and the falling phase of the internal clock signal,first and second variable delay circuits having delays thereof varied bythe results of phase comparison in the first and second phase detectioncircuits, the rising and fall of the internal clock signal, obtained onmultiplexing outputs of the first and second variable delay circuits,being adjustable independently of each other, a mode decision circuitfor determining the clock period and an initial delay value bycomparison, a first selection circuit for selecting for control of whichof the first and second variable delay circuits the result of phasecomparison by the first and second variable delay circuits is to beused, and

a second selection circuit for switching, in multiplexing signals outputfrom the first and second variable delay circuits to generate theinternal clock signal, between the use of the rise and the fall ofsignals output from the first and second variable delay circuits for therising of the internal clock signal and the use of the rise and the fallof signals output from the first and second variable delay circuits forthe fall of the internal clock signal, based on the result of modedecision.

A delay locked loop device for generating an internal clock signalsynchronized with an input clock signal, according to the presentinvention, comprises:

a first phase detection circuit for comparing the phase of the rise ofthe input clock signal and the phase of the rising of the internal clocksignal, a second phase detection circuit for comparing the phase of thefall of the input clock signal and the phase of the fall of the internalclock signal, first and second variable delay circuits, the delay ofwhich is varied by the result of phase comparison in the first andsecond phase detection circuits, the rise and fall of the internal clocksignal, obtained on multiplexing the outputs of the first and secondvariable delay circuits, being adjustable independently of each other,and a mode decision circuit for determining the clock period and aninitial delay value by comparison. The first phase detection circuitincludes changing means for comparing the phase of rising of theinternal clock signals to the phase of fall of the input clock signal bythe result of mode decision. The second phase detection circuit includeschanging means for comparing the phase of falling of the internal clocksignals to the phase of rising of the reference clock signal by theresult of mode decision. There is provided means for inverting the phaseof the internal clock by the result of mode decision.

In the delay locked loop device of the present invention, at least oneof the first and second phase detectors may be formed by a circuit fordetecting the duty ratio of the internal clock signal. Or, at least oneof the first and second phase detectors may be formed by a circuit fordetecting the duty ratio of the internal clock signal and a selectorcircuit controlled by the result of mode decision and the input dutyratio detection enable signal to select for control of which one of thefirst and second variable delay circuits the results of decision by thefirst and second phase detection circuits and by the duty ratiodetection circuit are used.

The meritorious effects of the present invention are summarized asfollows.

According to the present invention, low jitter and a small area may berealized in the development of the high-speed synchronous semiconductordevice.

According to the present invention, switching between e.g. the 1T modeand the 1.5T mode is possible in the high speed synchronoussemiconductor device, and an optimum synchronous mode may be realized,by a simplified structure, in accordance with the operating frequency.

Still other objects and advantages of the present invention will becomereadily apparent to those skilled in this art from the followingdetailed description in conjunction with the accompanying drawingswherein only the preferred embodiments of the invention are shown anddescribed, simply by way of illustration of the best mode contemplatedof carrying out this invention. As will be realized, the invention iscapable of other and different embodiments, and its several details arecapable of modifications in various obvious respects, all withoutdeparting from the invention. Accordingly, the drawing and descriptionare to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the configuration of an embodiment of adelay circuit according to the present invention.

FIG. 2 is a timing diagram for illustrating the embodiment of the delaycircuit according to the present invention.

FIGS. 3A to C are timing diagrams for illustrating the operating mode ofthe DLL, where FIG. 3A shows a 1T mode, FIG. 3B shows a 2T mode and FIG.3C shows a 1.5T mode.

FIG. 4 is a diagram showing the configuration of an embodiment of theDLL according to the present invention.

FIG. 5 is a diagram showing the configuration of an embodiment of adelay line circuit (CDL) according to the present invention.

FIG. 6 is a diagram showing the configuration of another embodiment of adelay line circuit (CDL) according to the present invention.

FIG. 7 is a diagram showing the configuration of still anotherembodiment of a delay line circuit (CDL) according to the presentinvention.

FIG. 8 is a diagram showing the configuration of a second embodiment ofthe DLL according to the present invention.

FIG. 9 is a diagram showing the configuration of a selector in thesecond embodiment of the DLL according to the present invention.

FIG. 10 is a diagram showing the configuration a multiplexer in thesecond embodiment of the DLL according to the present invention.

FIG. 11 is a diagram showing the configuration of a mode decisioncircuit in the second embodiment of the DLL according to the presentinvention.

FIG. 12 is a timing diagram for illustrating the operation of the 1Tmode in the second embodiment of the DLL according to the presentinvention.

FIG. 13 is a timing diagram for illustrating the operation of the 1.5Tmode in the second embodiment of the DLL according to the presentinvention.

FIG. 14 is a diagram showing the configuration of a third embodiment ofthe DLL according to the present invention.

FIG. 15 is a diagram showing the configuration of a selector in thethird embodiment of the DLL according to the present invention.

FIG. 16 is a diagram showing the configuration of a duty ratio detectioncircuit in the third embodiment of the DLL according to the presentinvention.

FIG. 17 is a diagram showing the configuration of a fourth embodiment ofthe DLL of the present invention.

FIG. 18 is a diagram showing the configuration of a fifth embodiment ofthe DLL of the present invention.

FIG. 19 is a diagram showing the configuration of a phase detector inthe fifth embodiment of the DLL of the present invention.

FIG. 20 is a diagram showing the configuration of a dummy circuit(BUF-SW) in the fifth embodiment of the DLL of the present invention.

FIG. 21 is a diagram showing the configuration of a conventional DLL(synchronous delay loop).

FIG. 22 is a diagram showing the configuration of the conventional DLL.

FIG. 23 is a diagram showing the configuration of a conventional delayline circuit.

PREFERRED EMBODIMENTS OF THE INVENTION

The preferred mode for carrying out the present invention is nowexplained. The present invention comprises a delay line circuit in whichthe propagation path for the rising edge and that for the falling edgeof an input signal are independently selected to provide for a variableduty ratio. By this delay line circuit, the DLL of, for example, x.5mode (1.5T mode if x=1) may be realized.

That is, if a mode (1.5T mode) in which a data output DQ by the delayfrom the rising edge (CLK↑) is synchronized with the fall of the clocksignal (CLK↓) (see “Rise propagation”) and the delay of the data outputDQ by the delay from the falling edge (CLK↓) is synchronized with therise of the clock signal (CLK↑) (see “Fall propagation”), as shown inFIG. 3C, can be set, the (maximum) propagation time may be shortened todiminish the jitter.

More specifically, a delay circuit according to a preferred embodimentof the present invention includes a first delay line circuit having aplurality of stages of delay units (inverters 101, 102, 103, . . . ,110, . . . ), a second delay line circuit having a plurality of stagesof delay units (NANDS 111, 112, 113, . . . , 110, . . . ), and aplurality of transfer circuits (131, 132, 133, . . . , 141, . . . )provided in association with respective stages of the delay units of thefirst delay line circuit. The transfer circuits performs control as towhether or not the transfer of the outputs (I1, I2, I3, . . . ) of theoutput delay units is to be made to associated stages of the delay unitsof the second delay line circuit. The delay units (111, 112, 113, . . .) of the respective stages of the second delay line circuit receiveoutputs of the transfer circuits (131, 132, 133, . . . ) provided inassociation with respective stages of the delay units and outputs (O1,O2, O3, O4, . . . ) of the delay units (112, 113, 114, 115 . . . )preceding to the delay units in question to send output signals to thefollowing stage delay unit or output ends (O0).

One of a plurality of the transfer circuits (131, 133, 135, 137, . . .), which respectively receive outputs (I0, I2, I4, I6, . . . ) ofeven-numbered stages of delay units of the first delay line circuit, isselected by a control signal (R_2, R_6, R_10, . . . ) associated withthe transfer circuit. One of a plurality of transfer circuits (132, 134,136, 138, . . . ), which respectively receive outputs (I1, I3, I5, I7, .. . ) of odd-numbered stages of delay units of the first delay linecircuit, is selected by a control signal (F_4, F_8, F_12, . . . )associated with the transfer circuit. The rise timing and the falltiming of an output signal O1 of the second delay line circuit arevariably set with respect to the rising and fall of the signal 10supplied to the first delay line circuit. The code of the set of controlsignals, supplied to the transfer circuits of the even-numbered andodd-numbered stages is preferably the thermometer code.

A modified embodiment of the present invention at least includes a delaycircuit, having a plural number of stages of delay units, such as 111 to115 of FIG. 7, a first switch which receives a selection control signaland is controlled to be on or off, such as N12 of FIG. 7, and a secondswitch, such as N11 of FIG. 7, which is connected to an output of adelay unit of the stage number in the delay units of the delay circuit,corresponding to the aforementioned selection control signal, and whichis turned on at a time point one of the rise and falling edges of theinput signal, supplied to and propagated through the delay circuit, hastraversed the number of stages corresponding to the selection controlsignal, to set a common node, such as MFE 11 of FIG. 7, to a first logicvalue. The modified embodiment of the present invention also includes asignal generating circuit, which is composed by such as transistors P21,P22 and an inverter INV7 of FIG. 7, and generates a rise or falling edgesignal responsive to transition of the common node from the first logicvalue to the second logic value, and a control circuit composed by suchas AND2, inverter INV8 and transistor P25 of FIG. 7, which sets thecommon node to the original first logic value responsive to the other ofthe rise and falling edges of the input signal supplied to the delaycircuit. In the present embodiment, one ends of the second set ofswitches such as N11 and N51 of FIG. 7, connected to outputs of pluraldelay units of respective different stages of the delay circuit, such asI1 and I5 of FIG. 7, are connected common to a common node, such as MFE11 of FIG. 7, and a first set of switches, such as N12 and N52 of FIG.7, which receives the selection control signal so as to be controlledon/off, are provided across the other ends of the second set of theswitches and a power supply corresponding to the second logic value.

In the present embodiment, it is also possible for the delay circuit tohave such a circuit configuration in which the delay units of the delaycircuit are constituted by inverters, the second set of switches and thefirst set of the switches are connected common to the common nodes forodd-numbered stages (MFE 11 and MFO 11), for the outputs of the delayunits of the odd-numbered stages, the second set of switches and thefirst set of the switches are connected common to the common nodes foreven-numbered stages (MRE 11 and MRO 11), for the outputs of the delayunits of the even-numbered stages, and delay of the rise and fall timingof the output are variably adjusted from the rise and fall timing of theinput.

Referring to FIG. 8, a delay synchronous loop (DLL) device according toa preferred embodiment of the present invention includes a variabledelay circuit (10) which receives an input signal and which variablydelays the rise and fall timing of the input signal to output theresultant signal, a multiplexing circuit (92) for outputting an outputsignal the pulse width of which is prescribed by the rise and fall ofthe signal delayed by the variable delay circuit 10, and a controlcircuit (12 and 13) for comparing the rise phase and the fall phase ofthe input signal with the rise phase and the fall phase of the outputsignal to variably control the delay time of the variable delay circuitbased on the result of the phase comparison. The multiplexing circuit(92) includes a circuit for switching between the decision of the risetiming and the fall timing of the output signal based on the rise andthe fall of the signal output from the variable delay circuit and thedecision of the rise timing and the fall timing of the output signalbased on the fall and the rise of the signal output from the variabledelay circuit, in accordance with the input mode decision signal. Thecontrol circuit varies the rise timing and the fall timing of the outputsignal in the variable delay circuit (10), based on the result of phasecomparison of the rise of the input signal and the rise of the outputsignal CLK_FDB and between the rise of the input clock signal and therise of the output signal, or varies the fall timing and the rise timingof the output signal in the variable delay circuit (10), based on theresult of phase comparison of the rise of the input signal and the riseof the output signal CLK_FDB and between the fall of the input signaland the fall of the output signal.

Preferably, the present embodiment includes a mode decision circuit 91for checking the operating mode, based on the result of phase comparisonoutput from the phase detector, determining the value of the modedecision signal and outputting the so determined signal value.

In a further embodiment of the present invention, shown in FIG. 14,there is provided a duty ratio detection circuit (93) for detecting theduty ratio of the feedback clock signal CLK_FDB in the DLL to output aduty ratio detection signal. The multiplexing circuit (92) switchesbetween the decision of the rise timing and the fall timing of theoutput signal based on the rise and the fall of the signal output fromthe variable delay circuit (10), and the decision of the fall timing andthe rise timing based on the fall and the rise of the signal output fromthe variable delay circuit, in accordance with the input mode decisionsignal M_SEL controlling the operating mode. The control circuit mayalso include a selector circuit (90 a) for selecting two of the firstresult of phase comparison PD_R0 of the rise of the input clock signalCLK and the rise of the feedback clock signal CLK_FDB in the first phasedetector (12 ₁), second result of phase comparison PD_F0 of the fall ofthe input clock signal CLK and the fall of the feedback clock signalCLK_FDB in the second phase detector (12 ₂) and the duty ratio detectionenable signal, based on a duty ratio detection enable signal DCCen andthe mode decision signal M_SEL, to vary the delay value of the risetiming and the fall timing of the output signal in the variable delaycircuit (10). When the control signal DCCen is in the inactive state,the selector (90 a) varies the delay value of the rise timing and thefall timing of the output signal in the variable delay circuit (10), inaccordance with the first result of phase comparison PD_R0 and thesecond result of phase comparison PD_F0, or varies the delay value ofthe rise timing and the fall timing of the output signal in the variabledelay circuit (10), in accordance with the second result of phasecomparison PD_R0 and the first result of phase comparison PD_F0, basedon the mode decision signal M_SEL. When the control signal DCCen is inthe active state, the selector (90 a) varies the delay value of the risetiming and the fall timing of the output signal in the variable delaycircuit (10), in accordance with the first result of phase comparisonPD_R0 and PD_DCC, or varies the delay value of the rise timing and thefall timing of the output signal in the variable delay circuit (10), inaccordance with the PD_DCC and PD_R0, based on the mode decision signalM_SEL.

A further embodiment of the present invention, shown in FIG. 18,includes a first delay circuit (10 ₁) having a variable delay time andoutputting a signal corresponding to an input clock signal the rising ofwhich has been delayed, a second delay circuit (10 ₂) having a variabledelay time and outputting a signal corresponding to an input clocksignal the falling of which has been delayed, a third delay circuit (15₁) receiving an output signal of the first delay circuit (10 ₁) andfinely adjusting the phase of the signal to output the resultant signal,a fourth delay circuit (15 ₂) receiving an output signal of the seconddelay circuit (10 ₂) and finely adjusting the phase of the signal tooutput the resultant signal. The further embodiment also includes amultiplexing circuit (92) receiving and multiplexing an output signal ofthe third delay circuit and an output signal of the fourth delay circuitto output a sole output clock signal, in which the multiplexing circuitoutputs, in accordance with an input mode decision signal M_SEL, anoutput clock signal CLK_0, the rise timing and the fall timing of whichare prescribed based on the rising and the fall of the input clocksignal, respectively, or an output clock signal CLK_0, the fall timingand the rise timing of which are prescribed based on the rising and thefall of the input clock signal, respectively. The present modificationalso includes a dummy circuit (95) for delay adjustment, for generatinga feedback clock signal CLK_FDB in phase with the output clock signaland a feedback clock signal CLK_FDB antiphase to the output clocksignal, based on the transition of the output clock signal CLK_0, andfor selecting one of the feedback clock signals as the feedback clocksignal CLK_FDB, based on the mode decision signal, a first phasedetector (94 ₁) for comparing the phase of the rising edges of the inputclock CLK and the feedback clock signal CLK_FDB to output a non-invertedresult of phase comparison and an inverted result of phase comparison tooutput one of the non-inverted result of phase comparison and theinverted result of phase comparison as the first result of phasecomparison PD_R0 based on the mode decision signal, a second phasedetector (94 ₂) for comparing the phase of the falling edges of theinput clock signal and the feedback clock signal to output anon-inverted result of phase comparison and an inverted result of phasecomparison to output one of the non-inverted result of phase comparisonand the inverted result of phase comparison as the second result ofphase comparison PD_F0 based on the mode decision signal, a firstcounter (13 ₁) for counting the first result of phase comparison, asecond counter (13 ₂) for counting the second result of phasecomparison, a first selection circuit (14 ₁) for outputting a controlsignal for adjusting the rise timing in the first delay circuit and asecond selection circuit (14 ₂) for outputting a control signal foradjusting the fall timing in the first delay circuit.

An embodiment of a delay circuit and an embodiment of a DLL circuit,according to the present invention, are hereinafter explained in detail.

EMBODIMENT OF THE INVENTION

FIG. 1 shows a structure of a delay circuit embodying the presentinvention. In this figure, I0 and O0 denote an input and an output,respectively, while R_2, R_6, R_10, R_14 and R_18 are rise controlsignals and F_4, F_8, F_12, F_16 and F_20 are fall control signals.Referring to FIG. 1, the delay circuit of the present embodimentincludes a first delay line circuit, composed of plural cascadedinverters 101, 102, . . . , and 110, a second delay line circuit,composed of plural cascaded NAND circuits 111, 112, 113, . . . , and121, and a set of transfer circuits, composed of plural NAND circuits131 to 141.

Of the set of transfer circuits, the NAND circuits 131, 133, 135, 137, .. . have first input ends connected to even-numbered stage inputs 10,12, 14, 16, . . . , of the first delay line circuit, respectively, whilehaving second input ends connected to the rise control signals R_2, R_6,R_10, R_14, . . . , respectively, and having output ends connected tofirst input ends of the NAND circuits 111, 113, 115, 117, . . . of thesecond delay line circuit respectively. The second input ends of theNAND circuits 111, 113, 115, 117, . . . of the second delay line circuitare connected to outputs O1, O3, O5, O7, . . . of the preceding stageNAND circuits 112, 114, 116, 118, . . . , respectively.

The NAND circuits 132, 134, 136, 138, . . . have first input endsconnected to odd-numbered stage outputs I1, I3, I5, I7, . . . , of thefirst delay line circuit, respectively, while having second input endsconnected to the fall control signals F_4, F_8, F_12, F_16, . . . , andhaving output ends connected to first input ends of the NAND circuits112, 114, 116, 118, . . . of the second delay line circuit respectively.The second input ends of the NAND circuits 112, 114, 116, 118, . . . ofthe second delay line circuit are connected to outputs O2, O4, O6, O8, .. . of the preceding stage NAND circuits 113, 115, 117, 119, . . . ,respectively.

From output nodes I1, I3, I5, . . . (=I2×i+1, i=0, 2, 3, . . . ) of theodd-numbered stages, falling edges are selected by control signalsF_(4×i+4) and supplied to corresponding stage NAND circuits of thesecond delay line circuit, while rising edges are selected by controlsignals R_(4×i+2) and supplied to corresponding NAND circuits of thesecond delay line circuit, so that the signal rise and the signal fallare multiplexed by the NAND circuits.

The control signals R_I (I=(4×i+2), i=0, 2, . . . ) for rising edges andthe control signals F_J (J=(4×i+4), i=0, 2, . . . ) for falling edgesmay be set independently, while thermometer codes, that is, the selectedcontrol signal and the control signals downstream thereof are High, withthe control signal ahead of the selected control signal is Low.

In FIG. 1, if e.g. the transfer circuits for I2 and I7 of the firstdelay line circuit are selected (with R_2 being Low, R_6, R_10 and R_14_. . . being High, F_4, F_8 and F_12 being Low and F_16, F_20, . . .being High), the outputs O0 to O10 of the respective delay units of thesecond delay line circuit are set to the rise timing and the fall timingshown in FIG. 2. The numbers affixed to the rising and falling edges ofthe operating waveform of FIG. 2 denote the numbers of stages of thegates as from the rise and fall of the input I0 (the number of gates ofthe first delay line circuit, transfer circuit and the second delay linecircuit). Referring to FIGS. 1 and 2, the circuit operation of thepresent embodiment is explained.

In FIG. 1, a rising edge, supplied from the input I0, is inverted by theinverter 101 and becomes the falling edge (see fall ‘1’ of I1 of FIG.2), and is further inverted by the inverter 102 to become a rising edge.Since the control signal R_6 is High, the NAND circuit 133 is responsiveto rising transition of the node 12 from Low to High to change itsoutput from High to Low. The output O2 of the NAND circuit 113, formingthe delay unit of the second delay line circuit, is responsive theretoand goes High from Low. That is, the output O2 rises with a delay offour delay time units as from the rising edge of the input I0 (see riseof O2 of FIG. 2 ‘4’).

An output of the NAND circuit 132, which receives the control signal F_4of Low level, is High, such that the output O1 of the NAND circuit 112undergoes a transition from High to Low responsive to the transition ofthe output O2 from Low to High. The output O1 falls with a delay of fivedelay time units as from the rising edge of the input I0 (see fall of O1of FIG. 2 ‘5’).

An output of the NAND circuit 131 which receives the control signal R_2of Low level, is High, such that the output O0 of the NAND circuit 111undergoes a transition from Low to High responsive to the transition ofthe output O1 from High to Low. The output O0 rises with a delay of sixdelay time units as from the rising edge of the input I0 (see fall of O0of FIG. 2 ‘6’). That is, the rising edge supplied from the input I0 tothe first delay line circuit is sent to the output O0 with a delay ofthe sum of the delay time (2×td) for two stages of the delay elements(inverters) of the first delay line circuit, the delay time (td) of thetransfer circuit 133 at the signal turning point and the delay time(3×td) for three stages of the delay elements (NANDs) of the seconddelay line circuit.

On the other hand, since the control signal R_10 is High, the NANDcircuit 135, which receives the signal as input, has its outputtransferred from High to Low, responsive to rising transition from Lowto High of the input I4, such that the output O4 of the NAND circuit 115transfers from Low to High. The output 4 rises with a delay of six delaytime units as from the rising edge of the input I0 (see rise of O4 ofFIG. 2 ‘6’).

Since the control signal F_8 is Low, the output of the NAND circuit 134is High. The NAND circuit 114 is responsive to rising transition of theoutput O4 to cause transition of the output O3 from High to Low. Thatis, the output O3 falls with a delay of seven time units from the risingedge of the input I0 (see fall of O3 of FIG. 2 ‘7’).

Similarly, the outputs O6, O8 and O10 of the second delay line circuitrise with a delay of 8, 10 and 12 delay time units as from the risingedge of the input I0, while the outputs O5, O7 and O9 of the seconddelay line circuit rise with a delay of 9, 11 and 13 delay time units asfrom the rising edge of the input I0 (see FIG. 2).

On the other hand, the falling edge supplied from the input I0 (see fallof I0 of FIG. 2 ‘0’) is inverted by the inverter 101 to become a risingedge (see rising of I1 of FIG. 2 ‘1’). The rising edge is furtherinverted by the inverters 102 to 107 to become a rising edge at I7.

Since the control signal F_16 is High, the NAND circuit 138, suppliedwith the output I7, as input, is responsive to the rising transition ofthe output I7 from the Low level to the High level, and causes thetransition of the output from the High level to the Low level. Theoutput O7 of the NAND circuit 118 transfers from the Low level to theHigh level. The output O7 rises with a delay of 9 delay time units fromthe falling edge of the input I0 (see rising of O7 of FIG. 2 ‘9’).

Since the control signal R_14 is High, the NAND circuit 137, suppliedwith the output I6, as input, is responsive to the falling transition ofthe output I6 from the High level to the Low level, to cause thetransition of the output from the Low level to the High level. Theoutput O6 of the NAND circuit 116 is responsive to transition of theoutput O7 from the Low level to the High level to transfer from the Highlevel to the Low level. The output O6 falls to a Low level with a delayof ten delay time units from the falling edge of the input I0 (seefalling of O6 of FIG. 2 ‘10’).

Since the control signal F_12 is Low, the output of the NAND circuit136, supplied with the output I5, as input, is Low1, such that theoutput O5 of the NAND circuit 116 is responsive to transition of theoutput O6 from the High level to the Low level to transfer from the Lowlevel to the High level. That is, the output O5 rises to a High levelwith a delay of 11 delay time units from the falling edge of the inputI0 (see falling of O5 of FIG. 2 ‘11’).

Since the control signal R_10 is High, the NAND circuit 135, suppliedwith the output I4, as input, is responsive to the falling transition ofthe output I4 from the High level to the Low level, to cause thetransition of the output from the Low level to the High level. Theoutput O4 of the NAND circuit 115 transfers from the High level to theLow level responsive to transition of the output O5 from the Low levelto the High level. The output O4 falls to a Low level with a delay of 12delay time units from the falling edge of the input I0 (see falling ofO4 of FIG. 2 ‘12’).

In similar manner, the outputs O3 and O1 rise to a High level with adelay of 13 and 15 delay time units from the falling edge of the inputI0. The outputs O2 and O0 fall to a Low level with a delay of 14 and 16delay time units as from the falling edge of the input I0, respectively.That is, the falling edge supplied from the input I0 to the first delayline circuit is sent to the output O0 with a delay of the sum of thedelay time (7×td) for seven stages of the delay elements (inverters) ofthe first delay line circuit, the delay time (td) of the transfercircuit 139 at the signal turning point and the delay time (8×td) foreight stages of the delay elements (NANDs) of the second delay linecircuit, that is, with a delay of 16 delay time units (16×td).

Since the control signal F_20 is High, the NAND circuit 140, suppliedwith the output I9, as input, is responsive to the transition of theoutput I9 from the Low level to the High level, to cause the transitionof the output from the High level to the Low level. The output O9 of theNAND circuit 120 transfers from the Low level to the High level. Theoutput O9 rises with a delay of 11 delay time units from the fallingedge of the input I0 (see rising of O9 of FIG. 2 ‘11’).

Since the control signal R_18 is High, the NAND circuit 139, suppliedwith the output I8, as input, is responsive to the transition of theoutput I8 from the High level to the Low level, to cause the transitionof the output from the Low level to the High level. The output O9 of theNAND circuit 119 is responsive to transition of the output O9 from theLow level to the High level to cause transition of the output O8 fromthe High level to the Low level. That is, the output O8 falls to the Lowlevel with a delay of 12 delay time units from the falling edge of theinput I0 (see rising of O8 of FIG. 2 ‘12’).

Since the control signal R_22 is High, the NAND circuit 141, suppliedwith the output I10, as input, is responsive to the transition of theoutput I10 from the High level to the Low level, to cause the transitionof the output from the Low level to the High level. The output O6 of theNAND circuit 116 is responsive to transition of the output O7 from theLow level to the High level, transfers from the High level to the Lowlevel. The NAND circuit 121 receives an output of the NAND circuit 141and O11 (fixed potential: High level) as inputs and, responsive to thefalling of the output of the NAND circuit 141, causes the output O10 tofall from a High level to a Low level with a delay of 12 delay timeunits from the falling edge of the input I0 (see falling of O10 of FIG.2 ‘12’).

Thus, by selecting the rise control signal R_6 (that is, by setting R_2to Low and by setting R_6, R_10, R_14, R_18 and R_22 to High) and byselecting the fall control signal R_16 (that is, by setting F_4, F_8 andF_12 to Low and by setting F_16 and F_20 to High), an output signal fromO1 is such a signal in which the rising edge thereof is delayed by 6delay time units from the rising of the input I0 and in which thefalling edge thereof is delayed by 16 delay time units from the fall ofthe input I0.

Thus, by suitably varying the selection of the rise control signal (R_2,R_6, R_10, R_14, R_18 and R_22) and the fall control signals (F_4, F_8,F_12, F_16 and F_20), the delay time as from the rising of the input I0until the rising of the signal from the output O0 and the delay time asfrom the fall of the input I0 until the fall of the signal from theoutput O0 may be varied independently of each other. That is, the pulsewidth and hence the duty ratio may be varied. Meanwhile, the number ofstages of the delay units in the first and second delay line circuits isarbitrary.

The delay circuit, shown in FIG. 1, realizes the 1.5T mode, by asimplified structure, and may be conveniently used in the DLL.

FIG. 4 shows an illustrative structure of the DLL employing a delaycircuit of the present embodiment. The DLL includes a first delaycircuit 10A (CDL) which receives an input clock signal and which hasvariable delays of the rising edge and the falling edge of an outputsignal, a second delay circuit 15 ₁ (FDL) which receives rising edges(O0_R and E0_R) of clock signals output from the first delay circuit 10A(CDL) to make fine adjustment of the output signal, and a third delaycircuit 152 (FDL) which receives falling edges (O0_F and E0_F) of clocksignals output from the first delay circuit 10A (CDL) to make fineadjustment of the output signal. The DLL also includes a multiplexer 16(MUX) which receives and multiplexes an output signal of the seconddelay circuit 15 ₁ and an output signal of the third delay circuit 15 ₂and a multiplexer 17 (data multiplexer) which receives a clock signalCLK_0 from the multiplexer 16 (MUX) and converts read data input inparallel into serial data in synchronization with the rise and fall ofthe clock signal to output the resulting serial data to a data outputterminal DQ. In FIG. 4, the reference numeral 17 denotes a data outputpath made up e.g. by a data multiplexer and an output buffer. The DLLalso includes a dummy circuit 18 (dummy multiplexer) having a delay timeequivalent to the delay time of the multiplexer 17, a first phasedetector PD(R) 12 ₁ which receives an input clock signal CLK and anoutput of the dummy circuit 18 and detects the phase difference of therising edges of the two input signals, and a second phase detector PD(R)12 ₂ which receives an input clock signal CLK and an output of the dummycircuit 18 and detects the phase difference of the falling edges of thetwo input signals. The DLL also includes a first counter 13 ₁ forperforming up/down counting of the result of phase comparison (UP/DOWN)output from the first phase detector 12 ₁ PD(R), a second counter 13 ₂for performing up/down counting of the result of phase comparison(UP/DOWN) output from the second phase detector 12 ₂ PD(R), a firstselection circuit 14 ₁ SEL(R) for outputting a control signal foradjusting the rise timing in the first selection circuit 10A based on acount output of the first counter 13 ₁ and a second selection circuit 14₂ SEL(F) for outputting a control signal for adjusting the fall timingin the first selection circuit 10A based on a count output of the secondcounter 13 ₂. The second delay circuit 15 ₁ (FDL) may be composed by aknown type of a phase interpolator for outputting an output signal of aphase corresponding to the division of a phase difference between risingedges of two signals (O0-R, E0-R). The third delay circuit 15 ₂ (FDL)may be composed by a known type of a phase interpolator for outputtingan output signal of a phase corresponding to the division of a phasedifference between falling edges of two signals (O0-F, E0-F). As for astructure of the FDL, see e.g. FIG. 1 of the aforementioned PatentPublication 1. It is noted that a dummy circuit of a delay timeequivalent to the delay of the input buffer 11 may be provided betweenthe dummy circuit 18 and the inputs of the phase detectors 12 ₁ and 12₂.

In FIG. 4, the first delay circuit 10A (R/F) is composed by a delaycircuit of the embodiment shown in FIG. 1. In the example in which e.g.the control signals R_6 and F_16 have been selected in FIG. 1, thepropagation paths of the input I0→output O0 of the rising edges and thefalling edges of the input I0, expressed by the number of gate stagesfrom the rise and fall of the input I0, in the operating waveform ofFIG. 2, are of 6 and 16 stages, respectively. That is, the duty ratiocan be variably set by varying the selected control signal.

Thus, in the DLL of this delay circuit, a data output from the dataoutput terminal DQ by the rising edge of the clock signal CLK may besynchronized with the fall of the clock signal of the next cycle, whilea data output from the data output terminal DQ by the falling edge ofthe clock signal CLK may be synchronized with the rise of the clocksignal of the next cycle.

That is, the 1.5T mode of FIG. 3C may be realized with the sole delaycircuit 10A. Meanwhile, not only the 1.5T mode but also x.5, where x isa number such that x>0, may also be realized in the present embodiment.

For application to a high precision DLL by the FDL (15 ₁ and 15 ₂ ofFIG. 4) which interpolates the phase difference corresponding to twogate stages (two stages of inverters forming delay units of the delaycircuit), two second delay line circuits of FIG. 1 are connected to thefirst delay line circuit made up by inverters 101 to 110, as shown inFIG. 5. In the present embodiment includes, as shown in FIG. 5, thereare provided a first delay line circuit (101 to 110), having pluralstages of the delay units (inverters), a first group of transfercircuits (121 to 129), a second delay line circuit (111 to 119) composedof plural delay units (NAND circuits), a second group of transfercircuits (141 to 147), and a third delay circuit (131 to 137) composedof plural delay units (NAND circuits). The number of stages of the delayunit in the respective delay circuits is arbitrary. The first group oftransfer circuits (121 to 129) and the second group of transfer circuits(141 to 147) are alternately supplied with a fall control signal (F_J)and with a rise control signal (R_I), as in the circuit shown in FIG. 1.The second delay line circuit and the third delay circuit output signals(O0_R, O0_F and E0_R, E0_F) which rise and fall with a delay of gatestages prescribed by the selected control signal from the rising edgeand the falling edge from the input I0. The delay circuit of FIG. 5 isapplied to the delay circuit 10A shown in FIG. 4, such that the risingedges O0_R and E0-R and the falling edges O0_F and E0-F are entered tothe FDLs 15 ₁ and 15 ₂ of FIG. 4, respectively. The structure shown inFIG. 5 is effective to simplify and reduce the size of the circuit. Byindependently selecting the propagation paths for the riding and fallingedges, in the delay circuit shown in FIG. 5, the duty cycle may be madevariable. Hence, the 1.5T mode may be realized to reduce the jitterwithout substantially increasing the area of the DLL delay circuit orthe operating current. By the way, the circuit block surrounded by abroken line in FIG. 5 (two inverters of the first delay line circuit,two NANDs of the associated second and third delay circuits and twotransfer circuits of each of the first and second groups of the transfercircuits) are made up by 36 transistors.

FIG. 6 shows the circuit configuration according to a further embodimentof the present invention. In the circuit shown in FIG. 6, the NANDcircuits 131 to 141 of the first group of transfer circuits of FIG. 1are composed by NOR circuits 171 to 181 and the NAND circuits 111 to 121of the second group of transfer circuits are composed by NOR circuits151 to 161. The rise control signals /R_2, /R_6, /R_10, /R_14 and /R_18and the fall control signals /F_4, /F_8, /F_12, /F_16 and /F_20 are allactive at a Low level. The operation of the delay circuit, shown in FIG.6, is basically the same as that shown in FIG. 1.

Another embodiment of the present invention is hereinafter explained.FIG. 7 shows the configuration of the other embodiment of a coarse delayline (CDL) according to the present invention. Referring to FIG. 7, thecoarse delay line (CDL) includes a multiplexer which receives signals ofpreset inverter stages of the delay circuit composed of a plural numberof inverter delay element stages and which selects an edge at a selectedinverter stage number of the inverter stages, out of the edgespropagated in the delay circuit, based on the input selection controlsignal, to output the so selected edge. Meanwhile, the structure shownin FIG. 7 outputs the rising edges O0_R and E0_R and the falling edgesO0_F and E0_F, as inputs to the FDLs 15 ₁ and 15 ₂ of FIG. 4. The risecontrol signals /R_5, /R_7, /R_9, /R_11 and the fall control signals/F_4, /F_6, /F_8 and /F_10, forming selection control signals for themultiplexer, are formed by binary codes. From the outputs of the oddinverter stages 11, 13, 15, 17, . . . of the first delay line circuit,formed by the inverter files 101 to 115, selection is made independently(separately) by the control signal F_j and outputs of the even inverterstages 12, 14, 16, . . . by R_i.

Referring to FIG. 7, the delay circuit CDL according to the presentembodiment includes a sole delay circuit having plural stages ofinverter files 101 to 105. A Nch transistor N11 which has a gateconnected to an output I1 of the delay circuit and which is controlledto be turned on or off, and a Nch transistor N12 which has a gatesupplied with a control signal F_4 and which is controlled to be turnedon or off, are connected in series across the ground and a common nodeMFE 11, whilst a Nch transistor 51 which has a gate connected to theinput I5 and which is controlled to be turned on or off, and a Nchtransistor N52 which has a gate supplied with the control signal F_8 andwhich is controlled to be turned on or off, are connected in seriesacross the ground and the common node MFE 11. A Nch transistor N31 whichhas a gate connected to an output I3 and which is controlled to beturned on or off, and a Nch transistor N32 which has a gate suppliedwith a control signal F_6 and which is controlled to be turned on oroff, are connected in series across the ground and a common node MFO 11,whilst a Nch transistor 71 which has a gate connected to the output I7and which is controlled to be turned on or off, and a Nch transistor N72which has a gate supplied with the control signal F_10 and which iscontrolled to be turned on or off, are connected in series across theground and the common node MFO 11. There is also provided a Pchtransistor P22 which has a source connected to the power supply via Pchtransistor P21 in the on-state, and has a gate connected to the commonnode MFE 11. The Pch transistor P22 has a drain connected to a commonnode MFE 2, and an inverter INV7 which has an input connected to thecommon node MFE2 and outputs an even falling signal E0_F.

There is also provided a Pch transistor P24 which has a source connectedto the power supply via Pch transistor P23 in the on-state and has agate connected to the common node MFO11. The Pch transistor P24 has adrain connected to the common node MFO2, and an inverter INV6 which hasan input connected to the common node MFO2 and outputs an odd fallingsignal O0_F.

There is provided a second AND circuit (AND2) having inputs connected tooutputs of inverters INV6, INV7 and the signal I0.

Pch transistors P25 and P26 are provided between the power supply andthe common nodes MFE11 and MFO11. An output of the AND2 is inverted byan inverter INV8 and supplied to the gates of the Nch transistors N3 andN4.

There are provided Nch transistors N3 and N4 across the common node MFE2and the ground and across the common node MFO2 and the ground,respectively. An output of the AND2 is supplied to the gates of the Nchtransistors N3 and N4.

If the input I0 falls from the High level to the Low level andsubsequently rises from the Low level to the High level, an output ofAND2 goes High to turn on the Nch transistors N3 and N4 to charge thecommon nodes MFE 11 and MFO 11 and to discharge the common nodes MFE 2and MFO 2. The above is the circuit for fall control. The rise controlcircuit is now explained.

A Nch transistor 21 which has a gate connected to an even number stageoutput I2 of the delay circuit and which is controlled to be on or off,is connected in series across the ground and the common node MRE 11,whilst a Nch transistor 61 which has a gate connected to the input I6and which is controlled to be on or off, and a Nch transistor 62 whichhas a gate supplied with the control signal R_9 and which is controlledto be on or off, are connected in series across the ground and thecommon node MRE 11. A Nch transistor 41 which has a gate connected tothe output I4 and which is controlled to be on or off, and a Nchtransistor 42, which has a gate supplied with the control signal R_7 andwhich is controlled to be on or off, are connected across the ground andthe common node MRO 11, whilst a Nch transistor 81 which has a gateconnected to the output I8 and which is controlled to be on or off, anda Nch transistor 82 which has a gate supplied with the control signalR_11 and which is controlled to be on or off, are connected in seriesacross the ground and the common node MRO 11.

There is provided a Pch transistor P12 which has a source connected tothe power supply via Pch transistor P11 in the on state and having agate connected to the common node MRE11. The drain of the Pch transistorP12 is connected to the common node MRE2. An even rising signal E0_R isoutput from an inverter INV5, inverting the output of an inverter INV2which has an input connected to the common node MRE 2.

There is provided a Pch transistor P14 which has a source connected tothe power supply via Pch transistor P13 in the on-state, and also has agate connected to the common node MRO 11. The drain of the Pchtransistor P14 is connected to the common node MRO 2, and an odd risingsignal O0_R is output from an inverter INV5 which inverts an output ofan inverter INV1 which has an input connected to the common node MRO2 t.

There is provided a first AND circuit (AND1) having inputs connected tooutputs of the inverters INV1 and INV2 and the input I0.

There are provided Pch transistors P15 and P16 across the power supplyand the common nodes MRE11 and MRO11. An output of the AND1 is invertedby inverter INV3 and supplied to the gates of the Pch transistors P15and P16.

There are provided Nch transistors N1 and N2 across the common node MRE2 and the ground and across the common node MRO2 and the ground,respectively, An output of the AND1 is supplied to the gates of the Nchtransistors N1 and N2.

At a time point when the input I0, which, after rising from the Lowlevel to the High level, has fallen to the Low level, the output of theAND1 goes High to turn on the Nch transistors N1 and N2 and the Pchtransistors P15 and P16 to charge the common nodes MRE 11 and MRO 11 aswell as to discharge the common nodes MRE2 and MRO2. The above is theexplanation on the fall control circuit.

Although not shown, the structure downstream of the output I9 of thedelay circuit is such that connection is made via switch to the commonnodes MFE11 and MFO11 via switch through a series circuit of transistorshaving gates connected to outputs of every fourth odd inverter stage anda transistor having a gate coupled to a control signal. Similarly, thestructure downstream of the output I10 of the delay circuit is such thatconnection is made via switch to the common nodes MFE11 and MFO11through a series circuit of transistors having gates connected tooutputs of every four odd inverter stage and a transistor having a gatecoupled to a control signal.

An example of the operation of the delay circuit, shown in FIG. 7, isnow explained. If, with the control signal R_5 High, the rising edge ofthe input I0 is propagated through the delay circuit, the common nodeMRE 11 is discharged, at a time point when the rising edge is propagatedthrough two inverter stages 101 and 102 in the delay circuit, throughthe Nch transistor N21, the gate of which is supplied with the input I2,and Nch transistor N22, the gate of which is supplied with the highlevel control signal R_5. This turns on the Pch transistor P12, the gateof which is supplied with the voltage of the node MRE 11, such that thecommon node MRE 2 is charged to the power supply potential VDD, invertedby the inverter INV2 to a Low level, and again inverted by the inverterINV5 to a High level to give the rise E0_R of an even output. In similarmanner, the rise O0_R of the odd output is output from the inverter INV4by selecting one of the control signals R_7 to R_11. Then, by the fallof the input I0 during the same clock cycle, an output of AND1 goes Highto turn on the Pch transistor P15, thus re-charging the common node MRE11 and re-discharging the node MRE2.

If, with the control signal F_9 High, the falling edge of the input I0is propagated through the delay circuit, the common node MFE 11 isdischarged, at a time point when the falling edge is propagated through7 inverter stages 101 to 107 in the delay circuit, through the Nchtransistor N71, the gate of which is supplied with the falling edge ofthe output I7, and the Nch transistor N72, the gate of which is suppliedwith the control signal F_10 in the High level. This turns on the Pchtransistor P22, the gate of which is supplied with the voltage of thenode MFE11, such that the common node MFE2 is charged to the powersupply potential VDD, and is inverted by the inverter INV7 to a Lowlevel, to give the rise E0_F of an even output. In similar manner, thefalling edge O0_F of the odd output is output from the inverter INV6 byselecting one of the control signal F_6 and F_10. Then, by the rising ofthe input I0 during the same clock cycle, the output of AND2 goes Highto turn on the Pch transistors P25 and P26 to re-charge the common nodeMFE 11 to the power supply voltage VDD as well as to re-discharge thenode MFE 2 to the ground potential. In this manner, the duty ratio maybe varied by varying the phase of the rise time.

With the present embodiment, described above, the rising phase and thefall phase of the output signal may be varied independently of eachother to vary the duty ratio.

In FIG. 7, the circuit structure for generating a signal supplied to theFDL of FIG. 4 is taken as an example for explanation. It is noted thateach one of the rising edges and the falling edges may be selected. Insuch case, the circuit structure is such a one in which the signal E0_Rand the signal E0_F, for example, are output.

By employing the delay circuits of the above-described embodiments asthe delay circuit 10A of FIG. 4, the 1.5T mode can be realized. That is,the above circuit helps reduce the current consumption as well as thechip area of the semiconductor memory devices, such as DDRII/I-SDRAM.

By supplying reference clock signals from e.g. a source frequencysynthesizer (PLL) to the input I0 of the delay circuit of each of theabove-described embodiments, and by varying the timing of the transitionedge of the clock, the frequency can be changed instantaneously torealize frequency modulation. The above-described embodiments may, ofcourse, be used as a variety of signal generating apparatus for variablysetting the fall time with respect to the reference signal.

FIG. 8 shows the configuration of a further embodiment of the presentinvention. The components which are the same as those shown in FIG. 22are indicated by the same reference numerals. The elements which are thesame as those of the conventional DLL circuit shown in FIG. 22 are notexplained here in order to avoid redundancy.

A first phase detector P/D(R) 12, compares the phase of the rising edgeof the input clock signal CLK with the phase of the rising edge of thefeedback clock signal CLK_FDB of the DLL circuit, also termed ‘internalclock signal’, and outputs a first phase comparison result signal PD_R0to a selector 90.

A second first phase detector P/D(F) 12 ₂ compares the phase of thefalling edge of the input clock signal CLK with the phase of the fallingedge of the feedback clock signal CLK_FDB, and outputs a second phasecomparison result signal PD_F0 to the selector 90.

The selector 90 receives a mode decision signal M_SEL, output from amode decision circuit 91, as a switching control signal, and determinesto which of first and second counters 13 ₁ and 13 ₂ the first phasecomparison result signal PD_R0 is to be supplied. The selector 90 alsomanages control to send the second phase comparison result signal PD_F0to the counter different from the counter supplied with the first phasecomparison result signal PD_R0.

The mode decision circuit 91 takes in the first phase comparison resultsignal PD_R0 and/or the second phase comparison result signal PD_F0,based on an input mode latch signal LAT, and decides on the operatingmode, based on one or the combination of the two signals, to output themode decision signal M_SEL

In the present embodiment, the 1.5T mode and 1T mode are realized whenthe mode decision signal M_SEL is High and Low, respectively.

The first CDL15 ₁ delays the rising edge of the clock signal, outputfrom the buffer 11, by delay time determined by the control signal, andoutputs a pair of signals O0_R and E0_R rising with different phase forthe duration of unit phases, such as, foe example, for two inverterstages. The second CDL15 ₂ delays the falling edge of the clock signal,output from the buffer 1, by delay time determined by the controlsignal, and outputs a pair of signals O0_F and E0_F rising withdifferent phase for the duration of unit phases, such as, for example,for two inverter stages.

A multiplexer circuit 92 includes a multiplexer, not shown, and aselection circuit, also not shown, for multiplexing a signal CLK_Routput from the first CDL15 ₁ and a signal CLK_F output from the secondCDL15 ₂, to a sole clock signal. The selection circuit manages controlto switch between input signal edges, prescribing the rising edge andthe falling edge of the clock signal CLK_0, based on the input modedecision signal M_SEL. That is, the rise timing of the clock signalCLK_0 is determined by the transition of one of the signals CLK_R andCLK_0, as selected by the selection circuit, based on the mode decisionsignal M_SEL, while the fall timing of the clock signal CLK_0 isdetermined by the transition of the other of the signals CLK_R andCLK_0.

A configuration of the selector 90, multiplexer circuit 92 and the modedecision circuit 91 of FIG. 9 is hereinafter explained.

FIG. 9 shows an illustrative structure of the selector 90 includingmultiplexers 901 and 902 each having first and second input terminalsfor receiving the first phase comparison result signal PD_R0 and thesecond phase comparison result signal PD_F0. When the mode decisionsignal M_SEL is Low, the multiplexer 901 selects and outputs the firstphase comparison result signal PD_R0, supplied to the first inputterminal thereof, as an output signal PD_R, while the multiplexer 902selects and outputs the second phase comparison result signal PD_F0,supplied to the second input terminal thereof, as an output signal PD_F.When the mode decision signal M_SEL is High, the multiplexer 901 selectsand outputs the second phase comparison result signal PD_F0, supplied tothe second input terminal thereof, as an output signal PD_R, while themultiplexer 902 selects and outputs the first phase comparison resultsignal PD_R0, supplied to the first input terminal thereof, as an outputsignal PD_F.

FIG. 10 shows the configuration of the multiplexer circuit 92. Referringto FIG. 10, the multiplexer circuit 92 includes two multiplexers 921 and922, each including first and second input terminals for receiving thesignal CLK_R output from the first CDL15 ₁ d and the signal CLK_F outputfrom the first CDL15 ₂, and an SR flip-flop 923 which has a set terminalconnected to an output of the multiplexer 921 and a reset terminalconnected to an output of the multiplexer 922.

With the mode decision signal M_SEL Low, the multiplexer 921 selects andoutputs the signal CLK_R supplied to the first input terminal, while themultiplexer 922 selects and outputs the signal CLK_F supplied to thesecond input terminal. The SR flip-flop 923 is set by the rising edge ofthe output of the multiplexer 921 to provide for the High level of theoutput CLK_0, while being reset by the rising edge of the output of themultiplexer 922 to provide for the Low level of the output CLK_0.

That is, the multiplexer circuit 92 outputs a clock pulse signal CLK_0having the rise and fall prescribed by the rise of the signals CLK_R andCLK_F.

When the mode decision signal M_SEL is High, the multiplexer 921 selectsand outputs the signal CLK_F, input to the second input terminalthereof, while the multiplexer 922 selects and outputs the signal CLK_R,input to the first input terminal thereof. The SR flip-flop 923 is setby the rising of the output from the multiplexer 921 (rising of thesignal CLK_F) to provide for a High level of the signal CLK_0, whilebeing reset by the rising of the output from the multiplexer 922 (risingof the signal CLK_R) to provide for a Low level of the signal CLK_0.That is, the multiplexer circuit 92 outputs a clock signal CLK_0, therising and fall of which are prescribed by the rise of the signal CLK_F(a signal corresponding to the input clock signal CLK the fall of whichhas been delayed) and by the rise of the signal CLK_R (a signalcorresponding to the input clock signal CLK the rise of which has beendelayed).

As described above, the multiplexer circuit 92 switches between a mode(1T mode) which, when the mode decision signal M_SEL is Low, generatesthe rising of the output signal CLK_0 from the rise of the CLK_R outputfrom the first CDL15 ₁ (hence from the rise of the input clock signalCLK), while generating the fall of the output signal CLK_0 from the riseof the signal CLK_F output from the second CDL15 ₂ (hence from the fallof the input clock signal CLK), and a mode (1.5T mode) which, when themode decision signal M_SEL is High, generates the fall of the outputsignal CLK_0 from the rise of the CLK_R output from the first CDL15 ₁(hence from the rise of the input clock signal CLK), while generatingthe fall of the output signal CLK_0 from the fall of the signal CLK_Foutput from the second CDL15 ₂ (hence from the fall of the input clocksignal CLK).

FIG. 11 shows the configuration of the mode decision circuit 91including a D type flip-flop 911. The first phase comparison resultsignal PD_R0 is sampled by the rise of a mode latch signal LAT andoutput as the mode decision signal M_SEL. For the mode latch signal LAT,a one-shot pulse, generated by e.g. a power-on-reset circuit, providedoutside of the DLL circuit, on power up of the device, or during theinitializing operation, such as on resetting.

FIGS. 12 and 13 are timing diagrams for illustrating the operation ofthe embodiment shown in FIG. 8. FIG. 12 is a timing chart showing theoperation when the mode decision signal M_SEL is Low. The operationcorresponds to the 1T mode operation explained with reference to FIG.3A.

The 1T mode operation of the present embodiment is now explained withreference to FIGS. 12 and 8. During the beginning time of the operation(initializing operation), the clock signal CLK_FDB is generated with adelay proper to the circuit as from the clock signal CLK. The firstphase detector 12, compares the phase of the rising edge of the clocksignal CLK_FDB to the phase of the clock signal CLK and, if, with thefirst phase comparison result signal PD_R0, the phase of the clocksignal CLK_FDB lags or leads the phase of the clock signal CLK, a Highlevel and a Low level are output as the phase comparison result signalPD_R0, respectively.

In the initializing operation of the DLL operation, the mode latchsignal LAT is output as a one-shot pulse. The mode decision circuit 91latches the first phase comparison result signal PD_R0 to output themode decision signal M_SEL.

In the example of FIG. 12, the first phase comparison result signalPD_R0 is Low when the mode latch signal LAT is output (when the one-shotpulse rises). That is, referring to FIG. 12, the clock signal CLK_FDB,fed back to the first phase detector 12, rises ahead of the rise timingof the clock signal of the next cycle to cycle of the clock signal CLKwith which the rising edge of the clock signal CLK_FDB was formed. Thus,the first phase detector 12, outputs the Low level as the first phasecomparison result signal PD_R0. Hence, the mode decision circuit 91,which samples the first phase comparison result signal PD_R0 with therising edge of the mode latch signal LAT, outputs a Low level as themode decision signal M_SEL to realize the 1T mode. With the 1T mode, theselector 90 outputs the first phase comparison result signal PD_R0 andthe second phase comparison result signal PD_F0 to the first counter (R)13 ₁ and to the second counter (R) 13 ₂, respectively.

A control signal from the first CDL(F) 10 ₁, the delay time of which isset variably, based on the control signal from the first counter (R) 13₁, has its delay value controlled so that the rising of the feedbackclock signal CLK_FDB is in phase with the rising of the input clocksignal CLK. A control signal from the second CDL(F) 10 ₂, the delay timeof which is set variably, based on the control signal from the secondcounter (F) 13 ₂, has its delay value controlled so that the fall of thefeedback clock signal CLK_FDB is in phase with the fall of the inputclock signal CLK.

The first FDL(F) 15 ₁ outputs an output signal CLK_R, with the finelyadjusted rising phase, based on the phase difference between the risingedges of the two signals O0_R and E0_R, output from the first CDL(F) 10₁.

The second FDL(F) 15 ₂ outputs an output signal CLK_F, with the finelyadjusted rising phase, based on the phase difference between the risingedges of the two signals O0_F and E0_F, output from the second CDL(F) 10₂.

The multiplexer circuit 92 performs switching control so that the risetiming of the clock signal CLK_R, delay-adjusted by the first FDL(F) 15₁, will be used for the rising of the clock signal CLK_0, and so thatthe rise timing of the clock signal CLK_F, delay-adjusted by the secondFDL(F) 15 ₂, will be used for the fall of the clock signal CLK_0. Thedelay value is adjusted by the first CDL(F) 10 ₁ so that the fallingedge of the feedback clock signal CLK_FDB, fed back to the phasedetector 12 ₁, will be coincident with the rising edge of e.g. the nextcycle clock signal CLK in the 1T mode, and so that the falling edge ofthe feedback clock signal CLK_FDB will be coincident with the fallingedge of e.g. the second next cycle clock signal CLK in the 1T mode.

FIG. 13 is a timing chart illustrating the operation of the circuit ofFIG. 8 in which the mode decision signal M_SEL is at a High level. Thisoperation is the 1.5T operation explained with reference to FIG. 3C. Theperiod of the clock signal CLK is shorter than that for the 1T modeshown in FIG. 12. Referring to FIGS. 13 and 8, the operation for the1.5T mode in the present embodiment is explained.

As in the 1T mode, the mode latch signal LAT is output only once duringe.g. the initializing operation of the DLL circuit. The mode decisioncircuit 91 latches the first phase comparison result signal PD_R0 tooutput the mode decision signal M_SEL.

In this case, the first phase comparison result signal PD_R0 is in aHigh level during e.g. the initializing operation of the DLL circuit.That is, since the clock signal period is shorter, as shown in FIG. 13,the feedback clock signal CLK_FDB, fed back to the phase detector 12 ₁,rises with a lag as from the rising of the input clock signal CLK of theclock cycle next following the cycle of the input clock signal CLK bywhich the clock signal CLK_FDB was formed. The phase comparison resultsignal PD_R0 is at a High level, and the mode decision circuit 91outputs a High level as a mode decision signal M_SEL to set up the 1.5Tmode.

In the 1.5T mode, the selector 90 is switched so that the first phasecomparison result signal PD_R0 and the second phase comparison resultsignal PD_F0 will be output to the second counter 13 ₂ and to the firstcounter 13 ₁, based on the mode decision signal M_SEL of the High level,respectively.

Based on the control signal, output from the first counter 13 ₁ (R), theCDL (R) 10 ₁ has its delay time controlled so that the fall of thefeedback clock signal CLK_FDB will be in phase with the rise of theclock signal CLK. Based on the control signal, output from the firstcounter 13 ₁ (R), the CDL (F) 10 ₂ has its delay time controlled so thatthe rising of the feedback clock signal CLK_FDB will be in phase withthe fall of the clock signal CLK. That is, in the 1.5T mode, the firstcounter 13 ₁ (R) varies the delay time of the first CDL 10 ₁ (R), basedon the second phase comparison result signal PD_F0 from the second phasedetector 12 ₂, detecting the falling phase difference between thefeedback clock signal CLK_FDB and the input clock signal CLK, while thesecond counter 13 ₂ (F) varies the delay time of the second CDL 102 (F),based on the first phase comparison result signal PD_R0 from the firstphase detector 12 ₁, adapted for detecting the rising phase differencebetween the feedback clock signal CLK_FDB and the input clock signalCLK.

The multiplexer circuit 92 generates the rising edge of the clock signalCLK_0, using the clock signal CLK_F, delay-adjusted by the FDL15 ₂ (F),while generating the falling edge of the clock signal CLK_0, using theclock signal CLK_R, delay-adjusted by the first FDL15 ₁ (R).

The fall timing of the output clock signal CLK_0 is adjusted by thefirst CDL10 ₁ (R) and the first FDL 15 ₁ (R), while the rise timing ofthe output clock signal CLK_0 is adjusted by the second CDL 10 ₂ (F) andthe second FDL 15 ₂ (R). The first CDL10 ₁ (R) has a delay value setbased on the output PD_F0 of the second phase detector 12 ₂ (result offalling edge phase detection of the input clock signal CLK and thefeedback clock signal CLK_FDB), while the second CDL10 ₂ (F) has a delayvalue set based on the output PD_R0 of the first phase detector 12 ₁(result of rising edge phase detection of the input clock signal CLK andthe feedback clock signal CLK_FDB).

In the present embodiment, as compared to the conventional semiconductorstorage device, providing only the 1T mode or the 2T mode, the delaylength from the fall of the clock signal CLK until the rising of thefeedback clock signal CLK_FDB may be shorter by one-half clock cycle, bythe 1T mode, as shown in FIG. 13, thereby reducing the delay variationcaused by noise, that is, jitter.

In the mode decision circuit 91, shown in FIG. 11, a mode decision isexecuted, using only the phase comparison result signal PD_R0, in orderto realize the least functions. However, the mode decision circuit 91is, of course, not limited to this configuration. The mode decisioncircuit 91 may be configured for latching the logical sum of the firstphase comparison result signal PD_R0 and the second phase comparisonresult signal PD_F0. Or, the mode decision circuit 91 may be configuredfor executing the mode decision by carrying out preset logicalcalculations of the first phase comparison result signal PD_R0 and thesecond phase comparison result signal PD_F0 with other control signals.

FIG. 14 shows the configuration of another embodiment of the DLL circuitaccording to the present invention. The present embodiment, shown inFIG. 14, includes a duty ratio detection circuit 93 (DCC), in additionto the structure of the embodiment shown in FIG. 8.

The duty ratio detection circuit 93 (DCC) receives the feedback clocksignal CLK_FDB to detect the duty ratio to output a duty ratio detectionsignal PD_DCC to a selector 90 a.

The selector 90 a is controlled by the mode decision signal M_SEL and byan input DCC enable signal DCCen, which validates the result of dutyratio detection, and selects two signals from the first phase comparisonresult signal PD_R0, second phase comparison result signal PD_F0 and thedetection signal PD_DCC, to transmit the selected signals to the firstcounter 13 ₁ (R) and the second counter 13 ₂ (F).

FIG. 15 shows the configuration of the selector 90 a shown in FIG. 14.Referring to FIG. 15, the selector 90 a includes two multiplexers 901,902, supplied at first and second input terminals thereof with the firstand second phase comparison result signal PD_R0 and PD_F0. Themultiplexers 901 and 902 select and output PD_R0 and PD_F0 when the modedecision signal M_SEL is at a Low level. The selector 90 a furtherinclude an AND circuit 903 which receives the mode decision signal M_SELand the DCC enable signal DCCen, an AND circuit 904 which receives aninverted version of the mode decision signal M_SEL and the DCC enablesignal DCCen, a multiplexer 905 which has first and second inputterminals supplied with an output of the multiplexer 901 and with theduty ratio detection signal PD_DCC, and a multiplexer 906 which hasfirst and second input terminals supplied with an output of themultiplexer 902 and with the duty ratio detection signal PD_DCC.

FIG. 16 shows the configuration of the duty ratio detection circuit DCC93 of FIG. 14. Referring to FIG. 16, the duty ratio detection circuitDCC 93 includes a charge pump circuit 931 and a comparator circuit 932.The charge pump circuit 931 charges a capacitance, not shown (such as aninternal node, e.g. a gate capacitance) during the High level period ofthe feedback clock signal CLK_FDB, and discharges the capacitance duringthe Low level period thereof. The comparator circuit 932 compares theterminal voltage of the capacitance of the charge pump circuit 931 to apreset reference voltage and outputs the result on which voltage ishigher as a duty ratio detection signal PC_DCC. As an alternativestructure of the duty ratio detection circuit DCC 93, the detectioncircuit may be configured for discharging (charging) a first capacitance(such as an internal node, e.g. a gate capacitance) during the Highlevel period of the feedback clock signal CLK_FDB, discharging(charging) a second capacitance of the same capacitance value as thefirst capacitance during the Low level period of the feedback clocksignal CLK_FDB, verifying which of the two capacitances is at a Highlevel and outputting the duty ratio detection signal PD_DCC. Of course,the duty ratio detection circuit DCC 93 may be formed using any othersuitable known circuits.

When the DCC enable signal DCCen and the mode decision signal M_SEL areat High levels (1.5T mode), the multiplexer 905 selects the PD_DCC and,otherwise, the multiplexer 906 selects an output of the multiplexer 901.

When the DCC enable signal DCCen is at a High level and the modedecision signal M_SEL is at a Low level, the multiplexer 906 selects thePD_DCC and, otherwise, a fourth multiplexer 909 selects an output of themultiplexer 902.

If, in the present embodiment, the DCC enable signal DCCen is at a Lowlevel and the duty ratio detection circuit DCC 93 is inactivated, theselector 90 a directly issues outputs of the multiplexers 901 and 902 assignals PD_R and PD_F, as in the selector 90 shown in FIG. 9. Theoperation is similar to that of the embodiment explained with referenceto FIG. 8.

If, in the present embodiment, the duty ratio detection circuit DCC 93is used, that is, if the DCC enable signal DCCen is High, dutycorrection may be carried out automatically by making adjustment forphase-matching the rising edge of the feedback clock signal CLK_FDB tothe rising edge of the clock signal CLK, and by employing the duty ratiodetection signal PD_DCC for the fall of the clock signal CLK.

For duty ratio correction, the falling edge of the feedback clock signalCLK_FDB may be phase-matched to the falling edge of the clock signalCLK-FDB, and the duty ratio detection signal PD_DCC may be used for therising edge of the clock signal CLK.

In the conventional DDR memory, the clock signal CLK_FDB isphase-matched to both the rise and falling edges of the clock signalCLK.

However, if the operation at a still higher speed is needed, it maypossibly become difficult to control the duty ratio of the clock signalCLK, and hence the duty ratio correcting function is needed.

The operation of the present embodiment will now be described. Theoperation for a case where the DCC enable signal DCCen is at a Low levelis the same as the operation of the embodiment shown in FIG. 8. That is,in the selector 90 a of FIG. 15, the outputs of the AND circuits 903 and904 are Low, with the operation of the selector being the same as thatof the selector 90 of FIG. 9.

When the DCC enable signal DCCen is Low and the mode decision signalM_SEL is Low (1T mode), the first phase comparison result signal PD_R0and the second phase comparison result signal PD_F0 are used forcontrolling the first CDL10 ₁ (R) and the second CDL10 ₂ (F),respectively. The rise timing of the feedback clock signal CLK_FDB isadjusted by the first CDL10 ₁ (R), and the fall timing of the feedbackclock signal CLK_FDB is adjusted by the second CDL10 ₂ (F).

When the DCC enable signal DCCen is Low and the mode decision signalM_SEL is High (1.5T mode), the second phase comparison result signalPD_F0 and the first phase comparison result signal PD_R0 are used forcontrolling the first CDL10 ₁ (R) and the second CDL10 ₂ (F),respectively. The rise timing of the feedback clock signal CLK_FDB isadjusted by the second CDL10 ₂ (F), which delays the fall of the inputclock signal CLK, while the fall timing of the clock signal CLK_FDB isadjusted by the first CDL10 ₁ (R), which delays the rising of the inputclock signal CLK.

When the DCC enable signal DCCen is High and the mode decision signalM_SEL is Low (1T mode), an output of the AND circuit 903 is Low and theoutput of the AND circuit 904 is High. The multiplexer 905 issues anoutput of the multiplexer 901, that is, the first phase comparisonresult signal PD_R0, as output signal PD_R, while the multiplexer 906issues PD_DCC as output signal PD_F. That is, the first phase comparisonresult signal PD_R0 is used for controlling the first CDL10 ₁ (R), whilethe duty ratio detection signal PD_DCC is used for controlling thesecond CDL10 ₂ (F). The rise timing of the clock signal CLK_FDB isadjusted by the first CDL10 ₁ (R), while the fall timing of the clocksignal CLK_FDB is adjusted by the second CDL10 ₂ (F).

When the DCC enable signal DCCen is High and the mode decision signalM_SEL is High (1.5T mode), an output of the AND circuit 903 is High andthe output of the AND circuit 904 is Low. The multiplexer 905 issuesPD_DCC, as output signal PD_R, while the multiplexer 906 issues anoutput of the multiplexer 902, that is, the first phase comparisonresult signal PD_R0, as output signal PD_F. That is, the duty ratiodetection signal PD_DCC is used for controlling the first CDL10 ₁ (R),while the first phase comparison result signal PD_R0 is used forcontrolling the second CDL10 ₂ (F). The rise timing of the feedbackclock signal CLK_FDB is adjusted by the first CDL10 ₁ (R), while thefall timing of the clock signal CLK_FD is adjusted by the first CDL10 ₁(R).

By the above control, the operation of the 1T mode and the 1.5T mode maybe realized even in case of addition of the duty ratio adjustmentfunction by the duty ratio detection circuit DCC 93.

In FIG. 17, the second phase detector 12 ₂ is omitted from the structureof FIG. 14, and the duty ratio detection signal PD_DCC from the dutyratio detection circuit DCC 93 is used for adjusting the rising.

The structure shown in FIGS. 14 and 15 is changed to a structure inwhich the duty ratio detection signal PD_DCC is connected to an inputterminal PD_F0 of the selector 90 a, whereby the operation similar tothat when the DCCen is High at all times is achieved. The operation ofthe present embodiment is similar to that of the above embodiment,explained with reference to FIGS. 14 and 15, in which DCCen is at Highlevel.

FIG. 18 shows the configuration of a further embodiment of the presentinvention. In the present embodiment, the selector 90 a, used in theprevious embodiment, is omitted, the output level of phase detectors 94₁, 94 ₂ is adapted to be reversible, the feedback clock signal CLK_FDB,as the subject of comparison, is also adapted to be reversible, andwhich of the rising and the fall of the clock signal is to be the othersubject of comparison may be selectable by the mode decision signalM_SEL.

FIG. 19 shows the configuration of the first phase detector 94 ₁ of FIG.18. Referring to FIG. 19, the first phase detector 94 ₁ includes a phasedetector 941 for detecting the phase difference between the input clocksignal CLK and the feedback clock signal CLK_FDB to output complementary(i.e. non-inverted and inverted) phase comparison detection signals, anda multiplexer 942 for selecting one of the non-inverted and invertedphase comparison detection signals, output from the phase detector 941,by the mode decision signal M_SEL, to output the selected signal as thephase comparison result signal PD_R0. The structure of the second phasedetectors 94 ₂ is similar to that of the first detector described above.However, the second phase detectors 94 ₂ receives an inverted version ofthe feedback clock signal CLK_FDB, and outputs the phase comparisonresult signal PD_F0.

When the mode decision signal M_SEL is at Low level, the first andsecond phase detectors 94 ₁, 94 ₂ output non-inverted phase comparisonresult signals as PD_R0 and PD_F0, respectively. When the mode decisionsignal M_SEL is at High level, the first and second phase detectors 94₁, 94 ₂ output inverted phase comparison result signals as PD_R0 andPD_F0, respectively.

FIG. 20 shows the configuration of a dummy circuit 95 (a buffer and aswitch circuit). By the edge of the clock signal CLK0, a buffer circuit951 generates rise and fall signals. The multiplexer 952 selects one ofthese signals by the mode decision signal M_SEL. When the mode decisionsignal M_SEL is Low, the multiplexer 952 selects the rising edge tooutput it as a signal CLK_FDB and, when the mode decision signal M_SELis Low, the multiplexer 952 selects the falling edge to output it as asignal CLK_FDB

When the mode decision signal M_SEL is Low, the first and second phasedetectors 94 ₁ and 94 ₂ output the rising edge phase comparison resultsignal PD_R0 of phase comparison of the clock signal CLK and thefeedback clock signal CLK_FDB and the falling edge phase comparisonresult signal PD_F0 of phase comparison of the clock signal CLK and thefeedback clock signal CLK_FDB, to the first and second counters 13 ₁,and 13 ₂, respectively. The first and second counters 13 ₁, 13 ₂ adjustthe delay time of the first and second CDL10 ₁ (R) and CDL10 ₂ (F). Themultiplexer circuit 92 outputs a signal CLK_0, the rising and the fallof which are prescribed by a signal corresponding to the input clocksignal CLK the rising and falling edges of which have beendelay-adjusted by the first CDL10 ₁ and the second CDL10 ₂ and by thefirst FDL15 ₁ and the second FDL15 ₂. The buffer switch 95, forming adummy circuit of the input and output buffers, outputs a signal CLK_FBDwhich rises with the rising edge of the signal CLK_0 when the modedecision signal M_SEL is at low level.

With the mode decision signal M_SEL at a High level, the first andsecond phase detectors 94 ₁ and 94 ₂ respectively output to the firstand second counters 13 ₁ and 13 ₂ an inverted version PD_R0 of the phasecomparison result signal of the rising edges of the clock signal CLK andthe feedback clock signal CLK_FDB and an inverted version PD_F0 of thephase comparison result signal of the falling edges of the clock signalCLK and the feedback clock signal CLK_FDB. The delay values of therising and falling edges of the first CDL10 ₁, and the second CDL10 ₂are adjusted based on count values of the first and second counters 13 ₁and 13 ₂.

The multiplexer circuit 92 outputs an output clock signal CLK_0 whichrises based on the falling edge of the input clock signal CLK (output ofthe second FDL 15 ₂) and which falls based on the rising edge of theinput clock signal CLK (output of the second FDL 15 ₁).

The buffer switch 95, constituting a dummy circuit for compensating thedelay time of e.g. the input buffer 11 or the output buffer 17 of theDLL circuit in a feedback loop of the DLL circuit, selects an invertedoutput of the buffer 951 when the mode decision signal M_SEL is High,and outputs, as the feedback clock signal CLK_FDB, a signal which fallswith the rising edge of the output clock signal CLK_0 and which riseswith the falling edge of the output clock signal CLK_0. The feedbackclock signal CLK_FDB is antiphase with respect to the output clocksignal CLK_0, the rising and the fall of which are prescribed by thefall and the rising of the input clock signal.

By the above-described structure, the mode in which the delay value inthe first CDL10 ₁ (R) is adjusted so that the rising edge of thefeedback clock signal CLK_FDB is coincident with the rising phase of theinput clock signal CLK and the delay value in the second CDL10 ₂ (F) isadjusted so that the falling phase of the feedback clock signal CLK_FDBis coincident with the falling phase of the input clock signal CLK, isswitched to the mode in which the delay value in the second CDL10 ₂ (F)is adjusted so that the rising edge of the feedback clock signal CLK_FDBis coincident with the falling edge of the input clock signal CLK andthe delay value in the first CDL10 ₁ (R) is adjusted so that the fallingedge of the feedback clock signal CLK_FDB (generated based on the risingof the output clock signal CLK_0) is coincident with the rising phase ofthe input clock signal CLK, and vice versa.

Although the present invention has so far been explained with referenceto the above-described embodiments, it is to be noted that the presentinvention comprises a variety of modifications or corrections, withoutbeing limited to the particular structure of the above-describedembodiments.

According to the present invention, the delay time of the rising andfall transition edges of an output signal as from the correspondingtransition edges of an input signal may be variably set, by a simplifiedstructure, whereby the increase in the power consumption or the circuitsize may be reduced to a minimum. According to the present invention,low jitter and a small area may be realized in the development of ahigh-speed synchronous semiconductor storage device, such asDDRII/I-SDRAM.

Moreover, according to the present invention, the 1T mode may beswitched to the 1.5T mode and vice versa with a sole DLL circuit by asimplified structure.

It should be noted that other objects, features and aspects of thepresent invention will become apparent in the entire disclosure and thatmodifications may be done without departing the gist and scope of thepresent invention as disclosed herein and claimed as appended herewith.

Also it should be noted that any combination of the disclosed and/orclaimed elements, matters and/or items may fall under the modificationsaforementioned.

1. A semiconductor device having a delay circuit, the delay circuitcomprising: a first delay line circuit having a plurality of stages ofdelay units; a second delay line circuit having a plurality of stages ofdelay units; a plurality of transfer circuits provided in associationwith respective stages of the delay units of said first delay linecircuit, said transfer circuits respectively receiving outputs of saidstages of the delay units of said first delay line circuit to controlthe transfer of the outputs of said delay units to associated stages ofthe delay units of said second delay line circuit; said delay unit ofeach stage of said first delay line circuit inverting a signal suppliedto said delay units and outputting the inverted signal; the delay unitof each stage of said second delay line circuit, including a logiccircuit receiving an output signal of the transfer circuit associatedwith the delay unit and an output signal of a preceding stage andoutputting the result of logical operation of the input signals to afollowing stage, one of a plurality of the transfer circuits, receivingrespective outputs of odd-numbered stages of delay units of said firstdelay line circuit, is selected by a corresponding control signal; oneof a plurality of transfer circuits, receiving respective outputs ofeven-numbered stages of delay units of said first delay line circuit, isselected by a corresponding control signal; and the rise timing and thefall timing of an output signal of said second delay line circuit arevariably set with respect to the rising and fall of the signal suppliedto said first delay line circuit.
 2. A semiconductor device having adelay circuit, the delay circuit comprising: a first delay line circuithaving a plurality of stages of delay units; a second delay line circuithaving a plurality of stages of delay units; a plurality of transfercircuits provided in association with respective stages of the delayunits of said first delay line circuit, said transfer circuitsrespectively receiving outputs of said stages of the delay units of saidfirst delay line circuit to control the transfer of the outputs of saiddelay units to associated stages of the delay units of said second delayline circuit; said delay unit of each stage of said first delay linecircuit inverting a signal supplied to said delay units and outputtingthe inverted signal; the delay unit of each stage of said second delayline circuit, including a logic circuit receiving an output signal ofthe transfer circuit associated with the delay unit and an output signalof a preceding stage and outputting the result of logical operation ofthe input signals to a following stage, in case the control signalsupplied to the transfer circuit associated with a given one of theeven-numbered stages and to the transfer circuit associated with a givenone of the odd-numbered stages is activated, the control signalssupplied to respective transfer circuits downstream of said transfercircuit are activated.
 3. A semiconductor device having a delay lockedloop circuit, The delay locked loop circuit comprising: a first delayline circuit receiving an input clock signal; a second delay linecircuit for performing fine phase adjustment of an output signal basedon the rising of the clock signal output from said first delay linecircuit; a third delay circuit for performing fine phase adjustment ofan output signal based on the falling of the clock signal output fromsaid first delay line circuit; a multiplexing circuit receiving anoutput signal of said second delay line circuit and an output signal ofsaid third delay circuit and outputting an output clock signalmultiplexed from said two output signals supplied thereto; a first phasedetection circuit receiving said input clock signal and an output clocksignal of said multiplexing circuit to detect the phase difference ofthe rising edges thereof; a second phase detection circuit receivingsaid input clock signal and an output clock signal of said multiplexingcircuit to detect the phase difference of the falling edges thereof; afirst counter for counting the result of phase detection by said firstphase detection circuit; a second counter for counting the result ofphase detection by said second phase detection circuit; a firstselection circuit for outputting a control signal for adjusting the risetiming in said first delay line circuit based on a count output of saidfirst counter; and a second selection circuit for outputting a controlsignal for adjusting the fall timing in said first delay line circuitbased on a count output of said second counter; wherein said first delayline circuit is a delay circuit comprising: a plurality of stages ofdelay units; a plurality of transfer circuits provided in associationwith respective stages of the delay units of said first delay linecircuit, said transfer circuits respectively receiving outputs of saidstages of the delay units of said first delay line circuit to controlthe transfer of the outputs of said delay units to associated stages ofthe delay units of said second delay line circuit; said delay unit ofeach stage of said first delay line circuit inverting a signal suppliedto said delay units and outputting the inverted signal.
 4. Thesemiconductor device according to claim 3, wherein said first delay linecircuit outputs a signal with plural rising edges of respectivedifferent phases, generated from said input signal, and another signalwith plural falling edges of respective different phases, generated froman inverted version of said input signal.
 5. A semiconductor devicehaving a delay locked circuit for generating an internal clock signalsynchronized with an input clock signal, said delay locked loop circuitcomprising: a first phase detection circuit for comparing the risingphase of said input clock signal and the rising phase of said internalclock signal; a second phase detection circuit for comparing the fallingphase of said input clock signal to the falling phase of said internalclock signal; first and second variable delay circuits having delaysthereof varied by the results of phase comparison in said first andsecond phase detection circuits; the rinsing and falling of saidinternal clock signal, obtained on multiplexing outputs of said firstand second variable delay circuits, being adjustable independently ofeach other; a mode decision circuit for deterring the clock period andan initial delay value by comparison; a first selection circuit forselecting for control of which of said first and second variable delaycircuits the results of phase comparison by said first and second phasedetection circuits are to be used; and a second selection circuit forswitching, in multiplexing signals output from said first and secondvariable delay circuits to generate said internal clock signal, betweenthe use of the rise and the fall of signals output from said first andsecond variable delay circuits for the rising of said internal clocksignal and the use of the raise and fall of signal output from saidfirst and second variable delay circuits for the fall of said internalclock signal, based on the result of mode decision.
 6. The semiconductordevice according to claim 5, wherein at least one of said first andsecond phase detection circuits is composed by a circuit for detectingthe duty ratio of said internal clock signal.
 7. The semiconductordevice according to claim 5, further comprising; a circuit for detectingthe duty ratio of said internal clock signal; and a selector circuit foroperating, based on the result of mode decision and an input duty ratiodetection enable signal, for selecting for control of which of saidfirst and second variable delay circuits the results of decision by saidfirst and second phase detection circuits and said duty ratio detectioncircuit are to be used.
 8. A semiconductor device having a delay lockedloop circuit, said delay locked loop circuit comprising; a first phasedetection circuit for comparing the phase of the rise of said inputclock signal and the phase of the rise of said internal clock signal; asecond phase detection circuit for comparing the phase of the fall ofsaid input clock signal and the phase of the fall of said internal clocksignal; first and second variable delay circuits, the delay of which isvaried by the results of phase detection circuits, wherein the rise andfall of said internal clock signal, obtained on multiplexing the outputsof said first and second variable delay circuits, are adjustableindependently of each other; and a mode decision circuit for determiningthe clock period and an initial delay value by comparison, wherein saidfirst phase detection circuit includes a switching circuit for selectingan inverting or no-inverting output result of the comparison of thephase of rising of said internal clock signal with the phase of risingof said input clock signal to compare the phase of rising of saidinternal clock signal with the phase of fall of said input clock signalby the result of mode decision, said second phase detection circuitincludes a switching circuit for selecting an inverting of non-invertingoutput result of the comparison of the phase of rising of said internalclock signal with the phase of rising of said input clock signal tocompare the phase of falling of said internal clock signal to the phaseof rising of said reference clock signal by the result of mode decision,and there being provided a circuit for inverting the phase of saidinternal clock based on said result of mode decision is provided.
 9. Asemiconductor device having a delay locked loop circuit, said delaylocked loop circuit comprising: a variable delay circuit receiving aninput signal and outputting the signal with a variable delay of the risetiming and the fall timing of said input signal; a multiplexing circuitfor outputting an output signal the pulse width of which is prescribedby the rising and the fall of the signal delayed by said variable delaycircuit; and a control circuit for comparing the phase of rise and thefall of said input signal and the phase of rise and the fall of saidoutput signal for variable controlling the delay time of said variabledelay circuit based on the respective results of phase comparison; saidmultiplexing circuit including a circuit for switching between thedecision of the rise timing and the fall timing of said output signal ofsaid variable delay circuit, based on the fall and the rise of theoutput signal from said variable delay circuit; said control circuitincluding a circuit for switching between varying the delay value of therise timing and the fall timing of the output signal in said variabledelay circuit based on the result of comparison of the rising phase ofsaid input signal and the rising phase of said output signal and on theresult of comparison of the falling phase of said input signal and thefalling phase of said output signal and varying the delay value of thefall timing and the rise timing of the output signal in said variabledelay circuit based on the result of comparison of the rising phase ofthe input signal and the rising phase of the output signal and on theresult of comparison of the fall phase of said input signal and the fallphase of said output signal.